AI-powered tool

AI Constraint Generator

Paste your Verilog or VHDL top-level module. The AI reads every port, identifies clock domains and interfaces, maps pins to your board, and writes the complete constraint file — annotated.

Quick examples
Configuration
Anthropic API Key
Key stays in your browser — never sent anywhere except Anthropic.
Paste your HDL module and click Generate
XDC
Waiting for your module
Paste a Verilog or VHDL top-level. The AI detects clocks, interfaces, async signals, and board pins automatically.

Supports .xdc .sdc .lpf .cst
Port analysis
Reads every port in your module. Infers clocks, resets, UART, SPI, I2C, LVDS, audio, and video signals from names and bit-widths. Handles bus notation like data[7:0].
Board pin mapping
Knows the exact PACKAGE_PIN assignments for 13 boards. Your clk port gets mapped to W5 on Basys3, E3 on Arty A7 — automatically, from verified schematics.
Correct exceptions
Applies set_false_path to UART, buttons, switches, LEDs, resets. Adds set_clock_groups between independent clock domains. Output is ready to drop into Vivado.