1st Place + Special Jury Award // SanDisk Hardware Hackathon // 100+ Teams
01 // The Challenge
Build an ISA-compliant out-of-order processor from scratch
Design a fully compliant RV32I processor that executes instructions out-of-order using Tomasulo's Algorithm. The processor must support speculative execution, precise exception handling, and pass the full RISC-V ISA compliance test suite. Target: timing closure at 250 MHz on Xilinx UltraScale+ fabric.
02 // Architecture
7-stage pipeline with out-of-order execution
Pipeline Stages // Data Path
S1
Fetch
PC + Branch Pred + I-Cache
S2
Decode
RV32I Decode + Register Read
S3
Issue
Reservation Station Alloc
S4
Execute
ALU + Branch + MUL/DIV
S5
Memory
D-Cache + Load/Store
S6
Write-Back
CDB Broadcast
S7
Commit
ROB Retire + Arch Update
The core implements a full out-of-order microarchitecture centered around Tomasulo's Algorithm. Instructions are fetched, decoded, and issued to reservation stations, bypassing register bottlenecks. The pipeline achieves deep execution without significant stalling through speculative execution backed by branch prediction.
Scheduling
Reservation Stations
Instructions wait in reservation stations until their source operands become available via CDB broadcasts. When all operands are ready, the instruction is issued to the appropriate functional unit.
Ordering
Reorder Buffer (ROB)
A circular buffer that tracks all in-flight instructions and ensures they commit in program order. Enables precise exceptions and rollback on branch misprediction.
Forwarding
Common Data Bus (CDB)
Results are broadcast on the CDB the moment they are computed, waking up dependent instructions in reservation stations without waiting for register file write-back.
Speculation
Branch Prediction
A 2-bit saturating counter predictor with a BTB (Branch Target Buffer) enables the fetch stage to continue speculatively past unresolved branches, minimizing pipeline bubbles.
03 // The Hard Bug
A 1-cycle race condition hidden under ROB pressure
During verification, we hit a subtle failure that only appeared under very specific conditions. It took 3 days to isolate. Here is the exact sequence of events.
Symptom
Random assertion failures on the register file consistency checker SVA. Only triggered when running constrained-random sequences with high ALU instruction density and the ROB at near-full capacity (28/32 entries occupied).
Root Cause
A RAW (Read-After-Write) hazard that manifested under back-to-back dependent ALU instructions. The scoreboard was correctly tracking in-flight instructions, but the CDB broadcast timing had a 1-cycle race condition with the reservation station wakeup logic. When a result was broadcast on the CDB in cycle N, a dependent instruction that was allocated to a reservation station in the same cycle N would miss the broadcast entirely.
Discovery
Isolated using constrained-random UVM stimulus specifically targeting ROB pressure scenarios. We wrote a custom sequence that held the ROB at 85-95% occupancy while continuously issuing dependent ALU pairs. The failure rate went from 1-in-10,000 to 1-in-50.
The Fix
Added a forwarding bypass from the CDB broadcast stage directly to the reservation station comparators in the same cycle. The wakeup logic now checks both the existing operand tags and the CDB output simultaneously, eliminating the 1-cycle window. Zero impact on critical path timing.
The processor was verified using a layered UVM testbench with separate agent, sequencer, driver, and monitor components for the instruction fetch interface and the memory subsystem. Coverage-driven verification ensured every pipeline hazard path was exercised.
Methodology
Constrained-Random
Randomized instruction sequences with constraints targeting specific hazard patterns: RAW/WAW/WAR chains, branch misprediction recovery, and exception handling under pipeline pressure.
Assertions
SVA Coverage
60+ SystemVerilog Assertions monitoring pipeline invariants, ROB consistency, CDB protocol compliance, and AXI interface handshaking at every stage boundary.