Archive Folder [ Dev Tyagi ]I build the silicon that makes AI fast.
Protocol.01FPGA.RTL.SystemSystem Active
Hardware Engineer / LOG [01] / Silicon / Defense
DEV
TYAGI.
—
MHz post-synth
UltraScale+
>—%
Functional coverage
SVA / constrained-rand
— GB/s
DMA throughput
PYNQ-Z2
—+
Engineers led
Army Design Bureau
RISC-V—SystemVerilog—AXI4—UVM—Tomasulo's Algorithm—Xilinx UltraScale+—250 MHz—1 GB/s DMA—FPGA Design—AI Accelerators—STA / Lint / DRC— RISC-V—SystemVerilog—AXI4—UVM—Tomasulo's Algorithm—Xilinx UltraScale+—250 MHz—1 GB/s DMA—FPGA Design—AI Accelerators—STA / Lint / DRC—
About / Skills
Section 01 / 05

Silicon meets
systems thinking

001

B.Tech ECE student at Vellore Institute of Technology, Chennai (2023–2027). Designing and verifying RTL at the intersection of microarchitecture, high-speed protocol implementation, and AI inference acceleration.

Out-of-order RISC-V processors, AXI4 DMA engines, neural network inference accelerators, built from specification through timing closure at 250 MHz on Xilinx UltraScale+ fabric.

As Head of Robotics Club, VIT Chennai, led 40+ engineers across hardware development, RTL reviews, and intercollegiate engineering competitions.

Location · Chennai, India  ·  N13.0827° / E80.2707°
HDL & Verification
SystemVerilogVerilogVHDLUVMSVAConstrained-RandomFunctional Coverage
RTL / Microarch
OOO ExecutionTomasulo's AlgorithmSuperscalar PipelinesHazard ResolutionClock GatingCDC
Protocols
AXI4AXI4-LiteAXI4-StreamAHBSPII2CUART
Tools
VivadoModelSimQuestaVCSXceliumPythonC/C++Tcl
Platforms
Zynq-7000UltraScale+Cortex-A9 PS/PLPYNQ-Z2
Experience
Section 02 / 05

Where I've shipped
real silicon

002
EXP.01
FPGA RTL Design Intern
Vicharak · Remote
  • Ported PicoRV32 RISC-V core to Shrike Lite FPGA, fitting execution within tight LUT/BRAM budgets the original configuration exceeded.
  • Replaced AXI4-Lite memory interface with a custom SPI protocol bridge for off-chip flash-backed instruction fetch; fabric logic utilisation cut by over 30%.
  • Authored SPI controller and memory-mapped bridge RTL from scratch in SystemVerilog.
Mar 2026 – Present
EXP.02
RTL Design Intern
IIT Palakkad
  • Designed RTL for a neural network inference accelerator on Xilinx Zynq-7000, mapping convolutional and fully-connected layer datapaths into PL with Cortex-A9 PS handling control flow.
  • Built AXI4-MM / AXI4-Stream interfaces for low-latency weight/activation DMA.
  • Implemented INT8/INT16 fixed-point datapaths on DSP/BRAM, holding inference accuracy within target bounds.
May 2026 – Jul 2026
EXP.03
Team Lead, FPGA Signal Processing
Army Design Bureau Collaboration · VIT Chennai
  • Built real-time DSP pipelines (FFT, FIR filtering, feature extraction) in Zynq PL for RF signal classification, coupled over AXI4/AXI-Stream with ARM Cortex-A9 PS.
  • Cut end-to-end system latency by 15% through RTL pipelining, CDC fixes, and datapath restructuring.
  • Led RTL reviews and integration testing across a 40+ member engineering team.
Jan 2026 – Present
Projects
Section 03 / 05

Hardware that
pushes limits

003

Build the core. Accelerate the core. Secure the core. Each project below feeds the next — a single research trajectory from ISA-compliant processor design through neural inference acceleration to line-rate hardware security.

"

"Dev is one of the most exceptional hardware engineers I've worked with. His ability to navigate from RTL design to post-synthesis timing closure is rare for someone at his stage."

— Arun Rahul, Principal Investigator, IIT Palakkad
1st Place + Special Jury Award · SanDisk Hardware Hackathon (100+ teams)
Out-of-Order Superscalar RISC-V Processor
Full superscalar RV32I OOO processor implementing Tomasulo's Algorithm — reservation stations, ROB, CDB. 7-stage pipeline with speculative execution and precise exception handling. Passed the full RISC-V ISA compliance test suite.
SystemVerilogUVMSVA VivadoModelSimUltraScale+
GitHub Repo ↗Case Study ↗
250
MHz post-synth
>95%
Func. coverage
↗
Hardware AI Accelerator
Mini-TPU: Systolic Array Accelerator
8×8 INT8 systolic array mapped to FPGA fabric for accelerated matrix multiplication. Features AXI4-Stream interfaces with auto-triggering on TLAST assertions, achieving timing closure at 100MHz on Zybo Z7-20.
SystemVerilogAXI4-Stream Systolic ArrayZybo Z7-20
Live systolic dataflow // weight-stationary // activations flow right, partial sums accumulate down
100
MHz on Z7-20
INT8
8×8 Array
↗
ASIC/SmartNIC IP
SentinelIC: DDoS Mitigation Engine
Line-rate hardware DDoS detection and mitigation engine designed as commercial-grade ASIC/SmartNIC IP. Built entirely in SystemVerilog for ultra-low latency packet inspection and malicious traffic filtering before software layers.
SystemVerilogSmartNIC IP Network SecASIC RTL
Line-Rate
Packet Filter
↗
Research Collaboration
DecodeForge: LLM Inference on FPGA
Hardware accelerator research targeting efficient LLM inference on resource-constrained FPGA fabric. Focused on weight quantization and on-chip memory bandwidth, reducing model footprint without sacrificing throughput at the RTL level.
SystemVerilogRTL Design LLM InferenceFPGA
Research
Collab
↗
2nd Place · FPGA Makeathon
High-Throughput AXI4 DMA Engine
AXI4-MM/Stream DMA engine with configurable burst lengths and interrupt-driven descriptor architecture. Sustained 1 GB/s throughput on PYNQ-Z2 under real AXI traffic, verified with SVA and constrained-random stimulus.
SystemVerilogAXI4-MM AXI4-StreamPYNQ-Z2SVA
1 GB/s
Sustained
↗
PMDC Motor Drive FPGA Simulation
Closed-loop PMDC motor drive on Zybo Z7-20 with internally-generated PWM chopper and multi-frequency preset switching. Real-time telemetry streamed over TCP via AXI DMA and lwIP to a Python live dashboard.
SystemVerilogZynq-7000 lwIPAXI DMAPythonPWM
devtyagi3909/pmdc-fpga-motor-control ↗
↗
ConstraintForge: FPGA Timing Constraint Library
Annotated XDC/SDC/LPF constraint templates covering 14+ interfaces (AXI4, SPI, DDR3, RGMII, HDMI, MIPI CSI-2) across Xilinx, Intel, Lattice, and Gowin. CI-validated via GitHub Actions on every commit.
TclPython XDC / SDC / LPFGitHub ActionsCI/CD
GitHub Repo ↗Live Site ↗ CI
14+
Interfaces
↗
Recognition
Section 04 / 05

Competing at
the bleeding edge

004
ACH.01 / Competition
1st
Place + Special Jury Award
Out-of-order RISC-V processor design. 100+ competing teams, RTL track.
SanDisk Hardware Hackathon
ACH.02 / Competition
2nd
Place · FPGA Makeathon
AXI4 DMA engine sustaining 1 GB/s on PYNQ-Z2, verified under real AXI traffic.
FPGA Makeathon
ACH.03 / Leadership
40+
Engineers Led
Head of Robotics Club at VIT Chennai. Hardware development, workshops, intercollegiate competitions.
VIT Chennai / Robotics Club
Education
B.Tech · Electronics and Computer Engineering
Vellore Institute of Technology
Chennai, India  ·  2023–2027
RISC-V Architecture VLSI Design Embedded Systems 2027
Contact
Section 05 / 05
005

Let's build
something real.

Open for full-time roles, internships, and research collaborations in FPGA/RTL design, RISC-V microarchitecture, and AI accelerator development.

Email
devtyagi3909@gmail.com
LinkedIn
linkedin.com/in/dev-tyagi3909
GitHub
github.com/devtyagi3909
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