RISCV-OOO-CORE ARCHITECTURE EXPLORER
DUAL-ISSUE OUT-OF-ORDER SUPERSCALAR RV32I · TOMASULO ALGORITHM
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1ST PLACE + JURY AWARD · SANDISK HACKATHON
CLICK A STAGE TO INSPECT ITS IMPLEMENTATION
CDB BROADCAST BUS
FETCH
2-WIDE
PC + IMEM
✓ VERIFIED
DECODE
2-WIDE
RV32I FULL
✓ VERIFIED
RENAME
RAT
32→64 PHYS
FREE LIST
✓ VERIFIED
DISPATCH
ISSUE QUEUE
RAW HAZARD
SCOREBOARD
✓ VERIFIED
EXECUTE
ALU × 2
CDB WRITE
WAKEUP
✓ VERIFIED
COMMIT
ROB
IN-ORDER
PRECISE EXC
IN PROGRESS
TARGET: 250 MHz · XILINX ULTRASCALE+ · 7-STAGE PIPELINE
SELECT A STAGE
Click any pipeline stage above to inspect its RTL implementation
DUAL-ISSUE DISPATCH — VERIFIED TIMING (from simulation)
aclk
issue0_valid
issue1_valid
broadcast_valid
DUAL ISSUE